1. Field of the Invention
The present invention relates to methods for characterizing sequential (electronic data storage) cells using interdependent setup and hold times such that the interdependent setup and hold times can be used during static timing analysis, and to static timing analysis tools utilizing interdependent setup and hold times to analyze circuit designs including the sequential cells.
2. Related Art
FIG. 1 illustrates a simplified representation of an exemplary digital integrated circuit design flow 100. At a high level, the process starts with the product idea in step 101. In designing an integrated circuit (IC), engineers typically rely upon computer-implemented tools to help create a circuit schematic design consisting of individual devices coupled together to perform a certain function. In one embodiment, these computer-implemented tools include electronic design automation (EDA) software 102, which can translate the circuit into a physical representation, i.e., a layout. When the layout is finalized, it can be used during tape-out 103. After tape out, fabrication 104 as well as packaging and assembly 105 can proceed to produce the integrated circuit (IC) 106, also called a chip.
Note that EDA software (also called EDA tools) 102 can perform a plurality of steps 110-119, which are shown in linear fashion for simplicity in FIG. 1. In an actual IC design process, various steps may be repeated until certain tests are passed. Moreover, these steps may occur in different orders and combinations. Therefore, these steps are described below for context and general explanation rather than as a specific, or recommended, design flow for a particular IC.
In step 110, engineers can describe the functionality that they want to implement in a system design, perform what-if planning to refine that functionality, and check the costs associated with the system design. Hardware-software architecture partitioning can occur in this step. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include Model Architect, Saber, System Studio, and DesignWare® products.
In step 111, the VHDL or Verilog code for modules in the system design, i.e. the logic design, can be written and then verified for functional accuracy (e.g. checked to ensure that the logic design produces the correct outputs). Exemplary EDA software products from Synopsys, Inc. that can be used in step 111 include VCS, VERA, DesignWare®, Magellan, Formality, ESP and LEDA products.
In synthesis and design for test step 112, the VHDL/Verilog code can be translated to a netlist. This netlist can then be optimized for the target technology. Additionally, tests for checking the finished IC can be designed and implemented. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include Design Compiler®, Physical Compiler, Test Compiler, Power Compiler, FPGA Compiler, Tetramax, and DesignWare® products.
In netlist verification step 113, the netlist can be checked for compliance with timing constraints (referred to herein as static timing analysis, which may also be utilized in steps 112, 114, 115 and 116, and possibly other steps in the EDA flow) and for correspondence with the VHDL/Verilog code. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include Formality, PrimeTime, and VCS products.
In design planning step 114, an overall floorplan for the chip is constructed and analyzed for timing and top-level routing. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include Astro and IC Compiler products.
In physical implementation step 115, the circuit elements of the logic design can be positioned and connected (generally called “place and route”). Exemplary EDA software products from Synopsys, Inc. that can be used in step 115 include the Astro and IC Compiler products.
In analysis and extraction step 116, the circuit function can be verified at a transistor level, thereby permitting what-if refinement. Exemplary EDA software products from Synopsys, Inc. that can be used in step 116 include AstroRail, PrimeRail, Primetime, NanoTime, and Star RC/XT products.
In physical verification step 117, various checking functions can be performed to ensure correctness for manufacturing, electrical issues, lithographic issues, and circuitry. Exemplary EDA software products from Synopsys, Inc. that can be used in step 117 include the Hercules product.
In resolution enhancement step 118, the layout can be manipulated to improve manufacturability of the design. Exemplary EDA software products from Synopsys, Inc. that can be used in step 118 include Proteus, ProteusAF, and PSMGen products.
In mask data preparation step 119, the “tape-out” data for production of masks for lithographic use can be generated. Exemplary EDA software products from Synopsys, Inc. that can be used in step 119 include the CATS® family of products.
Various steps described above, e.g. steps 112-116, require access to a standard cell library that includes standard cells (hereinafter called cells) as well as a database that stores certain integrated circuit (IC) information associated with those cells. This standard cell library can include thousands of cells usable in implementing an IC design. Exemplary standard cells could include flip-flops, logic gates, adders, or other IC devices commonly used in an IC design. Exemplary IC information can include cell pin capacitance, cell output delay, cell output slew, and cell output current. For sequential cells (e.g., flip-flops and latches), conventional standard cell libraries also include setup and hold timing constraint information.
Standalone Static timing analysis (STA) is typically performed during netlist verification (step 113, FIG. 1), and involves determining the validity of a user's circuit design by comparing its simulated performance against imposed performance constraints. The performance differences are measured at each sequential cell, and these performance differences are typically called slacks. Negative slack implies performance violation, i.e., the circuit design will fail to work if implemented in a physical integrated circuit form. A negative slack at a sequential cell results from not meeting the setup time or hold time of the sequential cell.
A simplified sequential cell 200 is illustrated in FIG. 2(A) for purposes of describing STA, and consists of a data input terminal D, a clock input terminal CLK, and an output terminal Q. Sequential cell 200 has two timing arcs (indicated by arrows in FIG. 2(A): one arc from the CLK input to the D input to annotate the setup and hold times, and another arc from the CLK input to the Q output to annotate the CLK-to-Q delay. In STA, D and CLK are referred to, respectively, as an endpoint and a startpoint. The implication of this terminology is that a timing path starts at CLK and ends at input terminal D.
A conventional STA tool reads in a circuit netlist, one or more cell libraries, assertions describing timing analysis guidance and/or constraints, and a clock period T. Actually, a design may have many clocks, each with its own clock period and description. FIG. 2(B) shows a timing path with a single clock T for simplicity. Note that the present invention described below also pertains to instances where the launch clock differs from the capture clock (they may also differ in frequency). An exemplary synchronous circuit 210 is shown in FIG. 2(B), and includes two sequential cells (e.g., D-type flip-flops), startpoint circuit 200-1 and endpoint circuit 200-2, and additional combinational circuitry (not shown) in the data path between startpoint circuit 200-1 and endpoint circuit 200-2. The STA tool analyzes each synchronous circuit 210 of the circuit design against timing constraints defined by the cell library associated with sequential cell 200 and, for example, the clock period T, and reports whether the circuit design performs as intended (i.e., whether all of the synchronous circuits meet the timing constraints, or whether one or more of the synchronous circuits violate the timing constraints). In particular, this analysis is accomplished by computing the worst setup slack (SS) and worst hold slack (HS) at every endpoint. Referring to FIG. 2(B), these slacks are computed as follows:SS=min(tC+T)−max(tL+tD+tS)  (1)HS=min(tL+tD)−max(tC+tH)  (2)where tC, tL, tD, tS, and tH refer, respectively, to the capture path delay, launch path delay, data path delay, setup time, and hold time of synchronous circuit 210, as illustrated in FIG. 2(B).
If a slack of an associated synchronous circuit is negative or nonnegative, it is said to be violated or satisfied, respectively. If a setup slack is violated, the circuit design can be made to operate correctly by slowing the circuit down, i.e., by increasing T. If a hold slack is violated, the circuit design will not function correctly.
Because nonnegative slacks are required not to have violations, equations 1 and 2 (above) can also be written, respectively, as follows:min(tC+T)−max(tL+tD)≧max(tS)  (3)min(tL+tD)−max(tC)≧max(tH)  (4)
These inequalities require a difference, called a skew, to be larger than or equal to a number, called a constraint, which is stored in the library associated with each sequential cell 200. These inequalities, therefore, can be rewritten as:min(setup skew)≧max(setup time)  (5)min(hold skew)≧max(hold time)  (6)
Note that the setup and hold skews refer to the time difference between the data and clock signals measured for each synchronous circuit, whereas the setup and hold times refer to the minimum required time difference such that the data is reliably captured and stored by the sequential cell.
A common approach to characterize setup time for a sequential cell is to examine the setup skew versus CLK-to-Q delay relationship at a fixed hold skew, which is called here the counterpart skew. The process is similar for hold time. These approaches are illustrated shown in FIGS. 3(A) and 3(B). According to “Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems”, V. Stojanovic and V. G. Oklobdzija, IEEE Journal of Solid-State Circuits, Vol. 34, No. 4, pp. 536-548, April 1999, three regions can be determined for both plots: stable, metastable, and failure regions. The stable region is defined as the region in which the CLK-to-Q delay is independent of the setup or hold skew. As the skew decreases, the CLK-to-Q delay starts to rise in an exponential fashion (see M. Shoji, Theory of CMOS Digital Circuits and Circuit Failures, Princeton University Press, 1992). If the skew is excessively small, the sequential cell (register) fails to latch the data. This region is called the failure region. The region between the stable and failure regions is referred to as the metastable region.
The setup and hold times cannot fall in the failure region since the sequential circuit is unable to latch the data in that region. The setup (hold) time is usually set to the setup (hold) skew where the stable region crosses over into the metastable region. There are different approaches to identify this crossover point (see “Comparative Analysis . . . ”, cited above). In some approaches, the crossover point is the time where a certain amount of degradation in the CLK-to-Q delay occurs. For example, a 10% degradation is assumed in FIGS. 3(A) and 3(B). In some other approaches, the crossover point is the time where the sum of the setup skew and CLK-to-Q delay is minimized.
The setup and hold times of a given sequential cell are not independent (see U.S. Pat. No. 6,584,598, which is incorporated herein in its entirety); rather, these constraints are a function of the counterpart skews (hold skew for setup time and setup skew for hold time). These dependences are illustrated in FIGS. 4(A) and 4(B). Note that the setup time decreases as the hold skew increases and the hold time decreases as the setup skew increases. Thus, the smallest setup and hold times occur when the counterpart skews are the largest.
The interdependence between the setup and hold times can intuitively be explained as follows. Since the CLK-to-Q delay is dependent of both the setup and hold skews, it can be allocated to either the setup or hold side. For example, if the setup skew is small, this skew dominates the degradation in the CLK-to-Q delay; hence, the hold skew must be relatively large. The same reasoning applies to the hold side. Existing characterization approaches typically ignore the interdependence of the setup and hold times. This strategy leads to two main issues:
Issue 1. If the counterpart skews are assumed to be unnecessarily large, the resulting setup and hold times are optimistic. If, however, the data waveform does not satisfy large counterpart skews, optimistic setup and hold times cause the circuit to fail despite not violating any of the individual constraints. Alternatively, if the counterpart skews are assumed to be unnecessarily small, the resulting setup and hold times are pessimistic. Both cases should be avoided as the optimistic case can cause circuit failures after fabrication whereas the pessimistic case can show as false violations during STA.
Issue 2. If this dependence is considered but not exploited, an opportunity to reduce the number of timing violations and improve the slack is missed. In U.S. Pat. No. 6,584,598 (cited above), the first issue is resolved by considering this interdependence. However, only one interdependent pair of setup and hold times is considered; therefore, the interdependence is not exploited to improve slacks.
The accuracy of the data in cell timing libraries is an important factor in determining maximum clock frequencies T at which a particular circuit design can operate. Specifically, as described above, the setup and hold time constraints of sequential cells are used to verify the timing of a synchronous circuit design. If characterization of the timing constraints is inaccurate, the results can be either highly optimistic or pessimistic. The optimistic case can cause a fabricated circuit to fail whereas the pessimistic case can unnecessarily degrade circuit performance, making it more difficult to achieve a target frequency.
Although the importance of library data accuracy is well known, current constraint characterization practices suffer from both optimism and unnecessary pessimism. These problems are mostly due to the independent characterization of timing constraints.
What is needed is a comprehensive methodology to interdependently characterize setup and hold times for sequential cells, and to exploit the resulting interdependent setup/hold pairs in STA.